030-031_EETE-VF

EETE SEPT 2013

TEST & MEASUREMENT JESD204B vs. Serial LVDS interface considerations for wideband data converters By George Diniz The JESD204A industry standard for serial interfaces was developed to address the problem of interconnecting the newest wideband data converters with other system ICs in an efficient and cost saving manner. The motivation was to standardize an interface that would reduce the number of digital inputs/outputs between data converters and other devices, such as FPGAs (field-programmable gate arrays) and SoCs (systems-on-chip), through the use of a scalable high-speed serial interface. Trends show that new applications, as well as advances in existing ones, are driving the need for wideband data converters with increasingly higher sampling frequencies and data resolutions. Transmitting data to and from these wideband converters poses a significant design problem as bandwidth limitations of existing I/O technologies force the need for higher pin counts on converter products. Consequently, systems PCB designs have become increasingly more complex in terms of interconnect density. The challenge is routing a large number of high-speed digital signals while managing electrical noise. The ability to offer wideband data converters with GS/s sampling frequencies, using fewer interconnects, simplifies the PCB layout challenges and allows for smaller form factor realization without impacting overall system performance. Market forces continue to press for more features, functionality, and performance in a given system, driving the need for higher data-handling capacity. The high-speed A/D converter and D/A converter-to-FPGA interface had become a limiting factor in the ability of some system OEMs to meet their nextgeneration data-intensive demands. The JESD204B serial interface specification was specifically created to help solve this problem by addressing this critical data link. Figures 1 and 2 show typical high-speed converter-to-FPGA interconnect configurations using JESD204A/B. The applications driving the need for JESD204B OFDM-based technologies such as LTE used in today’s wireless infrastructure transceivers use DSP blocks implemented on FPGAs or system-on-chip devices driving antenna array elements to generate beams for each individual subscriber’s handset. Each array element can require movement of hundreds of megabytes of data per second between FPGAs and data converters in both transmit or receive modes. Today’s software defined radios use advanced modulation schemes that can be reconfigured on-the-fly, and rapidly increasing channel bandwidths, to deliver unprecedented wireless data rates. Efficient, low power, low pin count FPGA to data converter interfaces in the antenna path play a critical role in their performance. Software defined radio architectures are integral to the transceiver infrastructure for multicarrier, multimode wireless networks supporting GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA. Medical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI), and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer’s system that can be solved by the more efficient JESD204B interface. Increasingly sophisticated pulse structures on today’s advanced radar receivers are pushing signal bandwidths toward 1 GHz and higher. Latest generation active electronically scaled array (AESA) radar systems may have thousands of elements. High bandwidth SERDES-based serial interfaces are needed to connect the array element data converters to the FPGAs or DSPs that process incoming and generate outgoing data streams. Choosing between Series LVDS and the JESD204B interface In order to best select between converter products that use either LVDS or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short comparison is provided in table 1. At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high-level George Diniz is Product Line Director for high-speed data converters at Analog Devices - www.analog.com Fig. 1 and Fig. 2: Typical high-speed converter-to-FPGA interconnect configurations using JESD204A/B interfacing (source: Xilinx). 30 Electronic Engineering Times Europe September 2013 www.electronics-eetimes.com


EETE SEPT 2013
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