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PROGRAMABLE LOGIC control logic is used for writing and reading to the data buffer. A barcode logic module contains the state machine to transmit data to the LED. Upon receiving the control signals, it reads the data buffer starting from address 0 and sends the read data serially to the LED. It also controls the duration of the serial data and uses the clock from the dynamic clock generator to sweep the frequencies of the LED signalling emitting rates. This design overcomes the problems of barcode scanners’ inability to read barcodes on an LCD by using an LED to transmit the information, effectively emulating the barcode reflection. At the heart of the design is the iCE40LM family of FPGAs, which include integrated SPI and I2C blocks to interface with virtually all mobile sensors and application processors. Detailed descriptions of each block are available so users can customise the design for use with alternative sensors. The design can generate different frequencies to match different barcode scanners on the market and is available as a full package including the barcode interface, Android driver, library and API support and, because of the FPGA base, can be quickly customised to user requirements. The result is the ability to implement paperless barcodes for digital coupons, gift cards, loyalty programmes and so on. Partitioning tool eases multi-FPGA-based prototyping Cadence Design Systems has added the Protium rapid prototyping platform to its System Development Suite, claiming a 4X increase in capacity versus the previous generation but more importantly, reducing prototype bring-up time by up to 70 percent versus competitive solutions. “Typically with competing solutions, designers use the implementation tools that are offered by the FPGA vendors, but these tools are only good for designs that fit into one FPGA. So designers have to rewrite their RTL to map it across multiple FPGAs, they must also remodel their memory, and it can take them up to three months to bring up the FPGA prototype” told us Frank Schirrmeister, Group Director at Cadence Design Systems and responsible for product management of the Cadence System Development Suite. “By adding a software platform that takes care of this automatically, we bring down the set up time to a few weeks”, he added. Built using Xilinx Virtex-7 2000T FPGAs, the Protium platform is Cadence’s second-generation FPGA prototyping platform for software development, it supports up to 100 million gates. Featuring Palladium flow compatibility is another key advantage of the tool, since according the company, 95% of emulation users are also using FPGA-based prototyping. The Protium platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimizations. It also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimizes the tedious and errorprone manual FPGA bring-up steps. Using the same bring-up flow for Palladium emulation and Protium rapid prototyping, designers can switch seamlessly between the two execution engines, for example to benefit from the deeper debug features of the emulation platform. Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria. Addressing this, Cadence has expanded the Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard. The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis. Cadence www.cadence.com 32 Electronic Engineering Times Europe September 2014 www.electronics-eetimes.com


EETE SEP 2014
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