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EETE SEP 2014

PROGRAMABLE LOGIC FlexTiles European project hints at reconfigurable 3D chips By Julien Happich Launched in 2011 by a consortium of industries, universities and research and technology organizations, and co-funded by the European Union under the Seventh Framework Programme, the three-year FlexTiles project is coming to fruition this year. Deliverables to be presented at a workshop during the 24th International Conference on Field Programmable Logic in Munich next September include an OVP-based (Open Virtual Platform) simulator and FPGA demonstrators for the heterogeneous many-core architecture that was developed by the nine project members across five countries. The consortium also came up with a complete toolchain for the use of the so-called FlexTiles architecture, which although proven as a concept and through hardware emulation, has yet to be integrated as a SoC. Coordinated by aerospace and defence French giant Thalès, the project’s main goal was to develop a programmable heterogeneous many-core platform which can be reconfigured on the fly to meet advanced processing needs such as surveillance drones or driverless cars. The efficient programming of multi-core architectures is critical for embedded systems on a tight power budget or simply to build energy-efficient supercomputers, Fig. 1: The FlexTiles concept: a dual layer 3D chip with many cores on one layer interconnected through a reconfigurable embedded FPGA layer. but the challenge remained an unresolved issue despite the growing number of cores being used in embedded systems. By 2020, many-core solutions are expected to boast in excess of a thousand processor cores, calling for truly self-adaptive programmability, a more efficient way to explore embedded system optimisation on-the-fly than what manually coded reconfiguration scenarios could offer. The FlexTiles concept consists of a 3D stack of 2 dies forming a chiplet – see figure 1 – including on one layer a number of 2D interconnected general purpose processors (GPPs) and accelerators such as DSPs and embedded FPGAs (the many-core layer), and on a second layer, a reconfigurable embedded FPGA managed by a dedicated controller. A virtualization layer on top of a kernel hides the heterogeneity and the complexity of the many-core platform from its programmer and fine-tunes the mapping of an application at runtime. The virtualization layer provides self-adaptation capabilities by dynamic relocation of application tasks to software on the many-core layer or to hardware on the reconfigurable layer. This self-adaptation is used to optimize load balancing, power consumption, hot spots and resilience to faulty modules. “The self-adaptive capabilities of the programmable heterogeneous many-core platform defined in the FlexTiles project are key to optimise priorities at runtime”, explained Dr Philippe Millet, senior research engineer & project manager at Thalès, and coordinator of the FP7 FlexTiles project. “With our programming methodology, application designers can decide what parameters can be used to map their application to the many cores, setting task priorities while managing power consumption, memory availability, or response latencies.” Millet added. “At run time, the reconfiguration controller and the application always know the status of the chip, what resources are available” added Marc Morgan from the Centre Suisse d’Electronique et de Fig. 2: The FlexTiles programming tool-flow makes it transparent for application developers to use the many-core heterogeneous architecture. 34 Electronic Engineering Times Europe September 2014 www.electronics-eetimes.com


EETE SEP 2014
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