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EETE SEP 2014

Follow-us on @EETimesEurope FPGAs meet NSA guidelines In recent announcements, Microsemi has been building on the secure-operation aspects of two of its programmabledevice families; now it adds further weight to that effort with an announcement based on National Security Administration (NSA) guidelines for specific operations. Microsemi says this announcement further validates the company’s FPGA security capabilities and simplifies information assurance system design. The company’s SmartFusion2 SoC FPGA and IGLOO2 FPGA product families are the first FPGAs to successfully complete the U.S. National Security Agency (NSA) Information Assurance Directorate (IAD) Secure Implementation Guidelines (SIG) document. The NSA IAD set out this process to provide an overview of design and data security features that are most relevant to a set of information assurance (IA) systems use models, and includes guidelines for security policies based on appropriate user scenarios. With clear implementation guidelines for using SmartFusion2 and IGLOO2 FPGA devices, defence system designers are better able to address and mitigate security threats in secure communications and cyber security applications. The Department of Defence (DoD) has positioned SIGs as a key element in the Trusted Systems and Networks (TSN) strategy. Microsemi www.microsemi.com AMC-format card hosts Xilinx Virtex-7 FPGA for wireless front-ends CommAgility’s AMC-V7 is a high performance FPGA-based interface and processing card in the compact Advanced Mezzanine Card (AMC) form factor. Based around a highdensity Xilinx Virtex-7 FPGA, the new module is aimed at LTE wireless front-end systems requiring multiple 10G CPRI links at up to rate option 8, as well as a range of other highperformance FPGA applications. A selection of fast, flexible I/O is included, configured for wireless applications. An IDT CPS-1848 Serial RapidIO (SRIO) Gen 2 switch supports SRIO V2.1 at up to 20 Gbps per port. The board also includes three front panel SFP+ optical interfaces that provide flexible high-speed links, and are configurable as CPRI, OBSAI, GigE, SRIO or other standards. An optional SRIO mini-SAS connector provides high-speed cabled connectivity. Timing and synchronisation is achieved via the front panel or backplane clock I/O, or optionally via GPS. No additional timing equipment is required, which reduces system complexity. The Virtex-7 FPGA is provided as a VX415T-2 device as the standard build, with options up to the VX690T-2 available for the highest performance applications. It is provided with two banks of DDR3 SDRAM, and a bank of flash memory for storing FPGA configurations and additional software. CommAgility www.commagility.com www.electronics-eetimes.com Electronic Engineering Times Europe September 2014 37


EETE SEP 2014
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