High Frequency CMOS reference signals at the calibration frequency. The cosine signal is generated with a small Look Up Table (LUT) of size 4K (K < 64 in practice). The sine signal is derived from the cosine by a simple delay of K. 2: The coefficients h0 and h1 are estimated adaptively from the extracted x0 and x1 signals using an LMS algorithm as shown in Figure 2. 3: The gain and timing errors are then computed from the linearized set of equations as derived from Equation 3. Once estimated, the gain and timing errors are used to feed a digital correction engine. The gain is compensated using a simple digital multiplier. The correction of the timing error is accomplished with a modified fractional delay filter 3. Polyphase and symmetry are exploited to reduce the implementation complexity of the filter. Both the estimation and correction engines operate at the sub-ADC sampling rate. Down-sampling can be envisioned for the estimation block for further optimization. Proof of concept A composite test signal consisting of: • a TM3.1, 20 MHz LTE carrier centered at 300 MHz, • and a 253.44 MHz, -35 dBFS calibration sine-wave, corresponding to S=1, K=8, P=2K, can be generated using the test setup shown in Figure 3. This setup provides very high dynamic range thanks to low noise and high linearity D/A converter 4 and DVGA 5. A commercially available 14-bits / 500-Msps TIADC that integrates high resolution tunable gain and timing errors is used. The ADC raw data was captured with an FPGA and processed with IDT’s calibration algorithm using Matlab® software. The gain and timing errors of the TIADC have been set to approximately 0.5 dB and 5 ps respectively to simulate a worst case situation. Figure 4 shows the power spectrums of the data before and after calibration. The LTE carrier image, at -80 dBFS before calibration, has been reduced by about 30 dB to -110 dBFS level after calibration. The calibration signal and its image have been completely cancelled by the extraction and cancellation algorithm. This performance has been achieved within about 200 μs convergence time. Figure 2: Background estimation of gain and timing errors through a 2-tap digital adaptive filter. Figure 3: Block diagram of the test setup. Figure 4: Power spectrums before (TOP) and after calibration (Bottom) with 300 MHz LTE carrier. Figure 5: Image rejection versus the LTE carrier center frequency with fixed calibration signal. 12 Microwave Engineering Europe March-April 2014 www.microwave-eetimes.com

MWEE MARAPR 2014

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